A Temperature-Aware Scheduling with Incremental Binding and Floorplanning for HLS

Modern Integrated Circuits’ reliability and performance mainly depends upon its temperature and power due to the continuous process scaling. The IC peak temperature depends upon the power density of the IC. Thus, a power-aware High-Level Synthesis technique concentrates on the overall power reduction and is not appropriate for temperature-aware IC design. The temperature-aware design technique requires optimization in all phases of design. This paper, proposes an effective temperature-aware scheduling with incremental binding for the IC design. In the proposed method,the temperature awareness is incorporated in both high-level and physical level synthesis. Comparison of the proposed method with other temperature-aware techniques in experimental analysis shows significant reduction of the peak temperature and power of the Integrated Circuit.